Re: [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
From: Nishanth Menon <nm@ti.com>
Date: 2020-09-08 16:36:48
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On 17:52-20200907, Roger Quadros wrote:
Enable USB0 port in high-speed (2.0) mode.
Am I right that this is a choice forced by serdes mux configuration selection? Might be good to document it (default speed is super-speed).
quoted hunk ↗ jump to hunk
The board uses lane 3 of SERDES for USB. Set the mux accordingly. Signed-off-by: Roger Quadros <redacted> --- .../dts/ti/k3-j7200-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+)diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0ecaba600704..5ce3fddbd617 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts@@ -42,6 +42,12 @@ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ + >; + }; }; &wkup_uart0 {@@ -145,3 +151,19 @@ idle-states = <SERDES0_LANE0_PCIE1_LANE0>, <SERDES0_LANE1_PCIE1_LANE1>, <SERDES0_LANE2_QSGMII_LANE1>, <SERDES0_LANE3_IP4_UNUSED>; }; + +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +};-- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
-- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel