[PATCH v5 30/80] drm/vc4: crtc: Clear the PixelValve FIFO on disable
From: Maxime Ripard <hidden>
Date: 2020-09-03 08:09:44
Also in:
dri-devel, lkml
Subsystem:
drm drivers, drm drivers and misc gpu patches, drm drivers for vc4, the rest · Maintainers:
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Dave Stevenson, Linus Torvalds
In order to avoid a stale pixel getting stuck on mode change or a disable / enable cycle, we need to make sure to flush the PV FIFO on disable. Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Hoegeun Kwon <redacted> Tested-by: Stefan Wahren <redacted> Signed-off-by: Maxime Ripard <redacted> --- drivers/gpu/drm/vc4/vc4_crtc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 4c23cf8aefb9..73d918706f7e 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c@@ -424,8 +424,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, if (vc4_encoder->post_crtc_disable) vc4_encoder->post_crtc_disable(encoder); - CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); - + vc4_crtc_pixelvalve_reset(crtc); vc4_hvs_atomic_disable(crtc, old_state); if (vc4_encoder->post_crtc_powerdown)
--
git-series 0.9.1
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