Re: [PATCH v4 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
From: Catalin Marinas <catalin.marinas@arm.com>
Date: 2020-08-21 12:08:53
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kvmarm
On Mon, Aug 03, 2020 at 01:31:27PM -0600, Rob Herring wrote:
quoted hunk ↗ jump to hunk
@@ -979,6 +980,14 @@ write_sysreg(__scs_new, sysreg); \ } while (0) +#define read_sysreg_par() ({ \ + u64 par; \ + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ + par = read_sysreg(par_el1); \ + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ + par; \ +})
I was about to queue this up but one more point to clarify: can we get an interrupt at either side of the PAR_EL1 read and the handler do a device read, triggering the erratum? Do we need a DMB at exception entry/return? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel