[PATCH 2/2] arm64: dts: ls104x: Add L1/L2 cache edac node
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: 2020-08-13 07:58:59
Also in:
linux-edac
Subsystem:
arm/freescale layerscape arm architecture, the rest · Maintainers:
Frank Li, Linus Torvalds
From: York Sun <redacted> The Cortex A53/A57 cores on the Layerscape LS104x SoCs support EDAC for the L1/L2 caches. Add the corresponding nodes for it. Signed-off-by: York Sun <redacted> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 +++++ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +++++ 2 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 3b641bd432295..de218f305031f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi@@ -838,6 +838,11 @@ optee { }; }; + edac-a53 { + compatible = "arm,cortex-a53-edac"; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + }; #include "qoriq-qman-portals.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index d4c1da3d4bde2..768fcfc44aee8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi@@ -800,6 +800,11 @@ optee { method = "smc"; }; }; + + edac-a57 { + compatible = "arm,cortex-a57-edac"; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; }; #include "qoriq-qman-portals.dtsi"
--
2.28.0
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