Re: [boot-wrapper][PATCH] aarch64: Enable SPE for the non-secure world
From: Mark Rutland <mark.rutland@arm.com>
Date: 2020-08-12 12:11:44
On Fri, Jul 31, 2020 at 10:44:43AM +0100, Alexandru Elisei wrote:
MDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the profiling buffer to use non-secure memory and to permit direct register accesses from the non-secure world. So far, we haven't programmed MDCR_EL3 explicitly even though there are other fields which reset to an UNKNOWN value. The majority of those, when cleared, allow lower exception levels to use the features they control; for the other fields we don't have support yet. Reset the register to zero with the exception of MDCR_EL3.NSPB. Signed-off-by: Alexandru Elisei <redacted> --- Tested on the model, with ARMv8.2 enabled and disabled (no SPE present).
Applied, thanks! Mark.
quoted hunk ↗ jump to hunk
arch/aarch64/boot.S | 11 +++++++++++ 1 file changed, 11 insertions(+)diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 74705cded338..f821b0175d4b 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S@@ -55,6 +55,17 @@ _start: msr cptr_el3, xzr // Disable copro. traps to EL3 + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #32, #4 + cbz x1, 1f + + // Enable SPE for the non-secure world. + ldr x1, =(0x3 << 12) + orr x0, x0, x1 + +1: msr mdcr_el3, x0 // Disable traps to EL3 + mrs x0, id_aa64pfr0_el1 ubfx x0, x0, #32, #4 // SVE present? cbz x0, 1f // Skip SVE init if not-- 2.28.0
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