Audio cores need specific clock rates which can't be simply obtained by
adjusting integer multipliers and dividers. HW for such cases supports
delta-sigma modulation which enables fractional multipliers.

Port H3 delta-sigma table to R40. They have identical audio PLLs.

Signed-off-by: Jernej Skrabec <redacted>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++++++++++++++++++----------
 1 file changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 23bfe1d12f21..84153418453f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c

@@ -45,18 +45,29 @@ static struct ccu_nkmp pll_cpu_clk = {
  * the base (2x, 4x and 8x), and one variable divider (the one true
  * pll audio).
  *
- * We don't have any need for the variable divider for now, so we just
- * hardcode it to match with the clock names
+ * With sigma-delta modulation for fractional-N on the audio PLL,
+ * we have to use specific dividers. This means the variable divider
+ * can no longer be used, as the audio codec requests the exact clock
+ * rates we support through this mechanism. So we now hard code the
+ * variable divider to 1. This means the clock rates will no longer
+ * match the clock names.
  */
 #define SUN8I_R40_PLL_AUDIO_REG        0x008

-static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
-                                  "osc24M", 0x008,
-                                  8, 7,        /* N */
-                                  0, 5,        /* M */
-                                  BIT(31),     /* gate */
-                                  BIT(28),     /* lock */
-                                  CLK_SET_RATE_UNGATE);
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+       { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+       { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },