Re: [PATCH v2 7/9] spi: spi-s3c64xx: Ensure cur_speed holds actual clock value
From: Tomasz Figa <tfiga@chromium.org>
Date: 2020-08-24 13:21:56
Also in:
linux-samsung-soc, linux-spi, lkml
On Mon, Aug 24, 2020 at 3:17 PM Lukasz Stelmach [off-list ref] wrote:
It was <2020-08-22 sob 14:43>, when Krzysztof Kozlowski wrote:quoted
On Fri, Aug 21, 2020 at 06:13:59PM +0200, Łukasz Stelmach wrote:quoted
cur_speed is used to calculate transfer timeout and needs to be set to the actual value of (half) the clock speed for precise calculations.If you need this only for timeout calculation just divide it in s3c64xx_wait_for_dma().I divide it here to keep the relationship between the value the variable holds and the one that is inside clk_* (See? It's multiplied 3 lines above). If you look around every single clk_get_rate() call in the file is divided by two.quoted
Otherwise why only if (cmu) case is updated?You are righ I will update that too. However, I wonder if it is even possible that the value read from S3C64XX_SPI_CLK_CFG would be different than the one written to it?
It is not possible for the register itself, but please see my other reply, where I explained the integer rounding error which can happen when calculating the value to write to the register.
quoted
You are also affecting here not only timeout but s3c64xx_enable_datapath() which is not mentioned in commit log. In other words, this looks wrong.Indeed, there is a reference too. I've corrected the message.
Thanks! Best regards, Tomasz
quoted
quoted
Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com> --- drivers/spi/spi-s3c64xx.c | 1 + 1 file changed, 1 insertion(+)diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 02de734b8ab1..89c162efe355 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c@@ -626,6 +626,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); if (ret) return ret; + sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG); --2.26.2-- Łukasz Stelmach Samsung R&D Institute Poland Samsung Electronics
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