[PATCH v2] arm64: dts: imx8qm: added lvds pwm
From: Oliver Graute <hidden>
Date: 2020-08-18 06:23:15
Also in:
linux-clk, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, common clk framework, nxp i.mx clock drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Frank Li, Sascha Hauer, Michael Turquette, Stephen Boyd, Abel Vesa, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add nodes for lvds pwms Signed-off-by: Oliver Graute <redacted> --- .../boot/dts/freescale/imx8-ss-lsio.dtsi | 84 +++++++++++++++++++ drivers/clk/imx/clk-imx8qxp.c | 14 +++- drivers/firmware/imx/scu-pd.c | 6 +- include/dt-bindings/clock/imx8-clock.h | 12 +++ 4 files changed, 112 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index c21e0818887b..be241813fbea 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi@@ -7,6 +7,90 @@ #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> +lvds0_subsys: bus@56240000 +{ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56240000 0x0 0x56240000 0x10000>; + + lvds0_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds0_ipg_clk"; + }; + + lvds0_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds0_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "lvds0_pwm_lpcg_clk", + "lvds0_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + }; + + lvds0_pwm: pwm@56244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x56244000 0x1000>; + clocks = <&lvds0_lpcg IMX_LPCG_CLK_0>, + <&lvds0_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>; + status = "disabled"; + }; +}; + +lvds1_subsys: bus@57240000 +{ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57240000 0x0 0x57240000 0x10000>; + + lvds1_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds1_ipg_clk"; + }; + + lvds1_lpcg: clock-controller@5724300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5724300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds1_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "lvds1_pwm_lpcg_clk", + "lvds1_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + }; + + lvds1_pwm: pwm@57244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x57244000 0x1000>; + clocks = <&lvds1_lpcg IMX_LPCG_CLK_0>, + <&lvds1_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>; + status = "disabled"; + }; +}; + lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>;
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index a6b690d94025..45b63ed06619 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c@@ -97,8 +97,6 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells); clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells); clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); - clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells); /* Connectivity */ clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
@@ -130,6 +128,18 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells); clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); +/*LVDS*/ + clks[IMX_LVDS0_PIXEL_CLK] = imx_clk_scu("lvds0_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS0_I2C0_CLK] = imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS0_I2C1_CLK] = imx_clk_scu("lvds0_i2c1_clk", IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS0_PWM0_CLK] = imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS0_PHY_CLK] = imx_clk_scu("lvds0_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_PHY, clk_cells); + clks[IMX_LVDS1_PIXEL_CLK] = imx_clk_scu("lvds1_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS1_I2C0_CLK] = imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS1_I2C1_CLK] = imx_clk_scu("lvds1_i2c1_clk", IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS1_PWM0_CLK] = imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_LVDS1_PHY_CLK] = imx_clk_scu("lvds1_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_PHY, clk_cells); + /* GPU SS */ clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells); clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
index e6ed965c2134..1c51a22bb72c 100644
--- a/drivers/firmware/imx/scu-pd.c
+++ b/drivers/firmware/imx/scu-pd.c@@ -136,8 +136,6 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "ftm", IMX_SC_R_FTM_0, 2, true, 0 }, { "lpi2c", IMX_SC_R_I2C_0, 4, true, 0 }, { "adc", IMX_SC_R_ADC_0, 1, true, 0 }, - { "lcd", IMX_SC_R_LCD_0, 1, true, 0 }, - { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 }, { "lpuart", IMX_SC_R_UART_0, 4, true, 0 }, { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 }, { "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 },
@@ -163,6 +161,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, + { "lvds0-pwm0", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 }, + { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, + { "lvds1-i2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 }, + { "lvds1-pwm0", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 },
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 003b0293c9b5..d8d07833fbc2 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h@@ -135,6 +135,18 @@ #define IMX_A72_CLK 191 #define IMX_SCU_CLK_END 192 +/*LVDS*/ +#define IMX_LVDS0_PIXEL_CLK 200 +#define IMX_LVDS0_I2C0_CLK 201 +#define IMX_LVDS0_I2C1_CLK 202 +#define IMX_LVDS0_PWM0_CLK 203 +#define IMX_LVDS0_PHY_CLK 204 +#define IMX_LVDS1_PIXEL_CLK 205 +#define IMX_LVDS1_I2C0_CLK 206 +#define IMX_LVDS1_I2C1_CLK 207 +#define IMX_LVDS1_PWM0_CLK 208 +#define IMX_LVDS1_PHY_CLK 209 + /* LPCG clocks */ /* LSIO SS LPCG */
--
2.26.0
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