[PATCH v4 09/10] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
From: Lars Povlsen <hidden>
Date: 2020-07-27 08:42:58
Also in:
linux-clk, linux-devicetree, linux-gpio, lkml
Subsystem:
arm/microchip (arm64) soc support, arm/microchip sparx5 soc support, the rest · Maintainers:
Conor Dooley, Nicolas Ferre, Claudiu Beznea, Steen Hegelund, Daniel Machon, Linus Torvalds
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Signed-off-by: Lars Povlsen <redacted> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 39 +++++++++++++---------- 1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index baf4176ce1dfe..161846caf9c94 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi@@ -72,20 +72,29 @@ timer { <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; - clocks: clocks { - #address-cells = <2>; - #size-cells = <1>; - ranges; - ahb_clk: ahb-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - sys_clk: sys-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <625000000>; - }; + lcpll_clk: lcpll-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000000>; + }; + + clks: clock-controller@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + clocks = <&lcpll_clk>; + reg = <0x6 0x1110000c 0x24>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; }; axi: axi@600000000 {
@@ -161,8 +170,6 @@ uart2_pins: uart2-pins { pins = "GPIO_26", "GPIO_27"; function = "uart2"; }; - }; - }; };
--
2.27.0
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