Re: [PATCH v9 2/7] iommu/arm-smmu: Add support for split pagetables

Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.

Signed-off-by: Jordan Crouse <redacted>
---

 drivers/iommu/arm-smmu.c | 21 ++++++++++++++++-----
 drivers/iommu/arm-smmu.h | 25 +++++++++++++++++++------
 2 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 8a3a6c8c887a..048de2681670 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c

@@ -555,11 +555,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
                        cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;
                        cb->ttbr[1] = 0;
                } else {
-                       cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
-                       cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID,
-                                                 cfg->asid);
+                       cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
+                               cfg->asid);
                        cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
-                                                cfg->asid);
+                               cfg->asid);

+
+                       if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
+                               cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+                       else
+                               cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
                }
        } else {
                cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;

@@ -824,7 +828,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,

        /* Update the domain's page sizes to reflect the page table format */
        domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
-       domain->geometry.aperture_end = (1UL << ias) - 1;
+
+       if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
+               domain->geometry.aperture_start = ~0UL << ias;
+               domain->geometry.aperture_end = ~0UL;
+       } else {
+               domain->geometry.aperture_end = (1UL << ias) - 1;
+       }
+
        domain->geometry.force_aperture = true;

        /* Initialise the context bank with our page table cfg */

diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index 38b041530a4f..5f2de20e883b 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h

@@ -168,10 +168,12 @@ enum arm_smmu_cbar_type {
 #define ARM_SMMU_CB_TCR                        0x30
 #define ARM_SMMU_TCR_EAE               BIT(31)
 #define ARM_SMMU_TCR_EPD1              BIT(23)
+#define ARM_SMMU_TCR_A1                        BIT(22)
 #define ARM_SMMU_TCR_TG0               GENMASK(15, 14)
 #define ARM_SMMU_TCR_SH0               GENMASK(13, 12)
 #define ARM_SMMU_TCR_ORGN0             GENMASK(11, 10)
 #define ARM_SMMU_TCR_IRGN0             GENMASK(9, 8)
+#define ARM_SMMU_TCR_EPD0              BIT(7)
 #define ARM_SMMU_TCR_T0SZ              GENMASK(5, 0)

 #define ARM_SMMU_VTCR_RES1             BIT(31)

@@ -347,12 +349,23 @@ struct arm_smmu_domain {

 static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg)
 {
-       return ARM_SMMU_TCR_EPD1 |
-              FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
-              FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
-              FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
-              FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
-              FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
+       u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
+               FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
+               FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
+               FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
+               FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
+
+       /*
+       * When TTBR1 is selected shift the TCR fields by 16 bits and disable
+       * translation in TTBR0
+       */
+       if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
+               tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;
+               tcr |= ARM_SMMU_TCR_EPD0;
+       } else
+               tcr |= ARM_SMMU_TCR_EPD1;