[PATCH 2/3] clk: zynqmp: Use firmware specific divider clock flags
From: Amit Sunil Dhamne <hidden>
Date: 2020-06-30 00:30:32
Also in:
linux-clk, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Rajan Vaja <redacted> Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <redacted> Signed-off-by: Amit Sunil Dhamne <redacted> --- drivers/clk/zynqmp/clk-zynqmp.h | 9 +++++++++ drivers/clk/zynqmp/divider.c | 16 +++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index d8e580b..ade5e9e 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h@@ -32,6 +32,15 @@ /* do not gate, ever */ #define ZYNQMP_CLK_IS_CRITICAL BIT(11) +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + enum topology_type { TYPE_INVALID, TYPE_MUX,
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 66da02b..f15d6b7 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c@@ -319,7 +319,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, /* struct clk_divider assignments */ div->is_frac = !!((nodes->flag & CLK_FRAC) | (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); - div->flags = nodes->type_flag; + div->flags = 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ? + CLK_DIVIDER_ONE_BASED : 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ? + CLK_DIVIDER_POWER_OF_TWO : 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ? + CLK_DIVIDER_ALLOW_ZERO : 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ? + CLK_DIVIDER_HIWORD_MASK : 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ? + CLK_DIVIDER_ROUND_CLOSEST : 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ? + CLK_DIVIDER_READ_ONLY : 0; + div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ? + CLK_DIVIDER_MAX_AT_ZERO : 0; div->hw.init = &init; div->clk_id = clk_id; div->div_type = nodes->type; --
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