Re: [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting
From: Matthias Brugger <matthias.bgg@gmail.com>
Date: 2020-06-29 20:49:24
Also in:
linux-devicetree, linux-iommu, linux-mediatek, lkml
On 29/06/2020 09:13, Chao Hao wrote:
MT8173 is different from other SoCs for MMU_CTRL register. For mt8173, its bit9 is in_order_write_en and doesn't use its default 1'b1.> For other SoCs, bit[12] represents victim_tlb_en feature and victim_tlb is enable defaultly(bit[12]=1), if we use "regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR", victim_tlb will be disabled, it will drop iommu performace. So we need to deal with the setting of MMU_CTRL separately for mt8173 and others.
My proposal to rewrite the commit message: The MMU_CTRL regiser of MT8173 is different from other SoCs. The in_order_wr_en is bit[9] which is zero by default. Other SoCs have the vitcim_tlb_en feature mapped to bit[12]. This bit is set to one by default. We need to preserve the bit when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the bit will be cleared and IOMMU performance will drop.
quoted hunk ↗ jump to hunk
Suggested-by: Matthias Brugger <matthias.bgg@gmail.com> Suggested-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Chao Hao <redacted> --- drivers/iommu/mtk_iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8299a3299090..e46e2deee3fd 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c@@ -543,11 +543,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) return ret; } + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
The read is only needed in the else branch.
if (data->plat_data->m4u_plat == M4U_MT8173) regval = F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; else - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); regval = F_L2_MULIT_HIT_EN |
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