Re: [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register

On Sat, 2020-06-20 at 10:03 +0800, Yong Wu wrote:

Hi Chao,

On Thu, 2020-06-18 at 19:49 +0800, chao hao wrote: 

quoted

On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote:

[snip]

quoted

quoted

quoted

 
 #define REG_MMU_MISC_CTRL			0x048
+#define F_MMU_IN_ORDER_WR_EN			(BIT(1) | BIT(17))
+#define F_MMU_STANDARD_AXI_MODE_BIT		(BIT(3) | BIT(19))
+
 #define REG_MMU_DCM_DIS				0x050
 
 #define REG_MMU_CTRL_REG			0x110

@@ -578,6 +581,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
 	}
 
+	if (data->plat_data->has_misc_ctrl) {

That's confusing. We renamed the register to misc_ctrl, but it's present in all
SoCs. We should find a better name for this flag to describe what the hardware
supports.

ok, thanks for you advice, I will rename it in next version.
ex:has_perf_req(has performance requirement)

quoted

Regards,
Matthias

quoted

+		/* For mm_iommu, it can improve performance by the setting */
+		regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+		regval &= ~F_MMU_STANDARD_AXI_MODE_BIT;
+		regval &= ~F_MMU_IN_ORDER_WR_EN;

Note: mt2712 also is MISC_CTRL register, but it don't use this
in_order setting.

As commented in v3. 0x48 is either STANDARD_AXI_MODE or MISC_CTRL
register. No need two flags(reset_axi/has_xx) for it.

something like:

regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
if (reset_axi) {
regval = 0;
} else {   /* MISC_CTRL */
if (!apu[1])
regval &= ~F_MMU_STANDARD_AXI_MODE_BIT;
if (out_order_en)
regval &= ~F_MMU_IN_ORDER_WR_EN;
}
writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);


[1] Your current patch doesn't support apu-iommu, thus, add it when
necessary.

ok, the patchset don't need to "if (!apu[1])", I will fix it in next
version. thanks

quoted

quoted

quoted

+		writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
+	}
+
 	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 			     dev_name(data->dev), (void *)data)) {
 		writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);

diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 1b6ea839b92c..d711ac630037 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h

@@ -40,6 +40,7 @@ struct mtk_iommu_plat_data {
 
 	/* HW will use the EMI clock if there isn't the "bclk". */
 	bool                has_bclk;
+	bool		    has_misc_ctrl;
 	bool                has_vld_pa_rng;
 	bool                reset_axi;
 	unsigned char       larbid_remap[MTK_LARB_NR_MAX];

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel