Re: [PATCH] driver/perf: Add PMU driver for the ARM DMC-620 memory controller.

On Thu, Mar 19, 2020 at 12:03:43PM -0700, Tuan Phan wrote:

   Please find my comments below.

     On Mar 19, 2020, at 8:16 AM, Mark Rutland <[1]mark.rutland@arm.com>
     wrote:
     Hi Tuan,

     On Tue, Mar 17, 2020 at 05:29:38PM -0700, Tuan Phan wrote:

       DMC-620 PMU supports total 10 counters which each is
       independently programmable to different events and can
       be started and stopped individually.

     Looking at the TRM for DMC-620, the PMU registers are not in a separate
     frame from the other DMC control registers, and start at offset 0xA00
     (AKA 2560). I would generally expect that access to the DMC control
     registers was restricted to the secure world; is that not the case on
     your platform?

     I ask because if those are not restricted, the Normal world could
     potentially undermine the Secure world through this (e.g. playing with
     training settings, messing with the physical memory map, injecting RAS
     errors). Have you considered this?

   => Only PMU registers can be accessed within normal world. I only pass
   PMU registers (offset 0xA00) to kernel so shouldn’t be problem.

Just a stylistic thing since there's been a bit of back-and-forth on this
patch, but please can you fix your email client configuration so that the
replies are threaded properly? '=>' is non-standard and it's pretty
hard to spot in a mass of C code. You can look at
Documentation/process/email-clients.rst for some information about
configuring common clients.

Apologies if this comes across as pedantic, but it makes a surprising
difference in how easy it is to keep up with the thread (at least to me).

Will

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