Thread (12 messages) 12 messages, 2 authors, 2020-03-18

Re: [PATCH V6 0/4] mailbox/firmware: imx: support SCU channel type

From: Leonard Crestez <hidden>
Date: 2020-03-12 23:09:44
Also in: lkml

On 2020-03-04 7:55 AM, Peng Fan wrote:
From: Peng Fan <peng.fan@nxp.com>

V6:
  Add Oleksij's R-b tag
  Patch 3/4, per https://www.kernel.org/doc/Documentation/printk-formats.txt
  should use %zu for printk sizeof

V5:
  Move imx_mu_dcfg below imx_mu_priv
  Add init hooks to imx_mu_dcfg
  drop __packed __aligned
  Add more debug msg
  code style cleanup

V4:
  Drop IMX_MU_TYPE_[GENERIC, SCU]
  Pack MU chans init to separate function
  Add separate function for SCU chans init and xlate
  Add santity check to msg hdr.size
  Limit SCU MU chans to 6, TX0/RX0/RXDB[0-3]

V3:
  Rebase to Shawn's for-next
  Include fsl,imx8-mu-scu compatible
  Per Oleksij's comments, introduce generic tx/rx and added scu mu type
  Check fsl,imx8-mu-scu in firmware driver for fast_ipc

V2:
  Drop patch 1/3 which added fsl,scu property
  Force to use scu channel type when machine has node compatible "fsl,imx-scu"
  Force imx-scu to use fast_ipc

  I not found a generic method to make SCFW message generic enough, SCFW
  message is not fixed length including TX and RX. And it use TR0/RR0
  interrupt.

V1:
Sorry to bind the mailbox/firmware patch together. This is make it
to understand what changed to support using 1 TX and 1 RX channel
for SCFW message.

Per i.MX8QXP Reference mannual, there are several message using
examples. One of them is:
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example,
when a four-word message is desired, only one of the registers
needs to have its corresponding interrupt enable bit set at the
receiver side.

This patchset is to using this for SCFW message to replace four TX
and four RX method.
Tested-by: Leonard Crestez <redacted>

My stress tests pass on imx8qxp with this patcheset, however performance 
is not greatly improved. My guess is that this happens because of too 
many interrupts.

Is there really a reason to enable TIE? Spinning on TE bits without any 
interrupts should be just plain faster.
Peng Fan (4):
   dt-bindings: mailbox: imx-mu: add SCU MU support
   mailbox: imx: restructure code to make easy for new MU
   mailbox: imx: add SCU MU support
   firmware: imx-scu: Support one TX and one RX

  .../devicetree/bindings/mailbox/fsl,mu.txt         |   2 +
  drivers/firmware/imx/imx-scu.c                     |  54 ++++-
  drivers/mailbox/imx-mailbox.c                      | 267 +++++++++++++++++----
  3 files changed, 260 insertions(+), 63 deletions(-)


base-commit: 770fbb32d34e5d6298cc2be590c9d2fd6069aa17

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help