Hi Lucas,

On Mon, Feb 24, 2020 at 06:23:51PM +0100, Lucas Stach wrote:

On Fr, 2019-12-06 at 11:52 +0200, Laurentiu Palcu wrote:

quoted

This patch adds the node for iMX8MQ Display Controller Subsystem.

Signed-off-by: Laurentiu Palcu <redacted>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index f6e840c..da7e485 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi

@@ -981,6 +981,31 @@
                              interrupt-controller;
                              #interrupt-cells = <1>;
                      };
+
+                     dcss: display-controller@32e00000 {

Node address is lower than the irqsteer node, so the dcss node should
be added before, not after the irqsteer node in the DT.

That's correct, I'll move it.

quoted

+                             #address-cells = <1>;
+                             #size-cells = <0>;
+                             compatible = "nxp,imx8mq-dcss";
+                             reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+                             interrupts = <6>, <8>, <9>;
+                             interrupt-names = "ctx_ld", "ctxld_kick", "vblank";
+                             interrupt-parent = <&irqsteer>;
+                             clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+                                      <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+                                      <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+                                      <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+                                      <&clk IMX8MQ_CLK_DISP_DTRC>;
+                             clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+                             assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+                                               <&clk IMX8MQ_CLK_DISP_RTRM>,
+                                               <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+                             assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+                                                      <&clk IMX8MQ_SYS1_PLL_800M>,
+                                                      <&clk IMX8MQ_CLK_27M>;
+                             assigned-clock-rates = <800000000>,
+                                                        <400000000>;

Second line is not aligned to the first one.

ack

Thanks,
laurentiu

quoted

+                             status = "disabled";
+                     };
              };

              gpu: gpu@38000000 {

-- 
Laurentiu
NXP

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