[PATCH V3 2/4] mailbox: imx: restructure code to make easy for new MU
From: peng.fan@nxp.com
Date: 2020-02-26 04:46:57
Also in:
lkml
Subsystem:
mailbox api, the rest · Maintainers:
Jassi Brar, Linus Torvalds
From: Peng Fan <peng.fan@nxp.com> Add imx_mu_generic_tx for data send and imx_mu_generic_rx for interrupt data receive. Add 'type' for MU type. With these, it will be a bit easy to introduce i.MX8/8X SCU type MU dedicated to communicate with SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V3: New patch, restructure code. drivers/mailbox/imx-mailbox.c | 100 ++++++++++++++++++++++++++++-------------- 1 file changed, 67 insertions(+), 33 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 2cdcdc5f1119..901a3431fdb5 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c@@ -36,7 +36,17 @@ enum imx_mu_chan_type { IMX_MU_TYPE_RXDB, /* Rx doorbell */ }; +enum imx_mu_type { + IMX_MU_TYPE_GENERIC, +}; + +struct imx_mu_priv; +struct imx_mu_con_priv; + struct imx_mu_dcfg { + enum imx_mu_type type; + int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); + int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); u32 xTR[4]; /* Transmit Registers */ u32 xRR[4]; /* Receive Registers */ u32 xSR; /* Status Register */
@@ -67,20 +77,6 @@ struct imx_mu_priv { bool side_b; }; -static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { - .xTR = {0x0, 0x4, 0x8, 0xc}, - .xRR = {0x10, 0x14, 0x18, 0x1c}, - .xSR = 0x20, - .xCR = 0x24, -}; - -static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { - .xTR = {0x20, 0x24, 0x28, 0x2c}, - .xRR = {0x40, 0x44, 0x48, 0x4c}, - .xSR = 0x60, - .xCR = 0x64, -}; - static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) { return container_of(mbox, struct imx_mu_priv, mbox);
@@ -111,6 +107,40 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) return val; } +static int imx_mu_generic_tx(struct imx_mu_priv *priv, + struct imx_mu_con_priv *cp, + void *data) +{ + u32 *arg = data; + + switch (cp->type) { + case IMX_MU_TYPE_TX: + imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); + imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); + break; + case IMX_MU_TYPE_TXDB: + imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); + tasklet_schedule(&cp->txdb_tasklet); + break; + default: + dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); + return -EINVAL; + } + + return 0; +} + +static int imx_mu_generic_rx(struct imx_mu_priv *priv, + struct imx_mu_con_priv *cp) +{ + u32 dat; + + dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); + mbox_chan_received_data(cp->chan, (void *)&dat); + + return 0; +} + static void imx_mu_txdb_tasklet(unsigned long data) { struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
@@ -123,7 +153,7 @@ static irqreturn_t imx_mu_isr(int irq, void *p) struct mbox_chan *chan = p; struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; - u32 val, ctrl, dat; + u32 val, ctrl; ctrl = imx_mu_read(priv, priv->dcfg->xCR); val = imx_mu_read(priv, priv->dcfg->xSR);
@@ -152,8 +182,7 @@ static irqreturn_t imx_mu_isr(int irq, void *p) imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); mbox_chan_txdone(chan, 0); } else if (val == IMX_MU_xSR_RFn(cp->idx)) { - dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); - mbox_chan_received_data(chan, (void *)&dat); + priv->dcfg->rx(priv, cp); } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); mbox_chan_received_data(chan, NULL);
@@ -169,23 +198,8 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data) { struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; - u32 *arg = data; - - switch (cp->type) { - case IMX_MU_TYPE_TX: - imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); - imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); - break; - case IMX_MU_TYPE_TXDB: - imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); - tasklet_schedule(&cp->txdb_tasklet); - break; - default: - dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); - return -EINVAL; - } - return 0; + return priv->dcfg->tx(priv, cp, data); } static int imx_mu_startup(struct mbox_chan *chan)
@@ -367,6 +381,26 @@ static int imx_mu_remove(struct platform_device *pdev) return 0; } +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { + .type = IMX_MU_TYPE_GENERIC, + .tx = imx_mu_generic_tx, + .rx = imx_mu_generic_rx, + .xTR = {0x0, 0x4, 0x8, 0xc}, + .xRR = {0x10, 0x14, 0x18, 0x1c}, + .xSR = 0x20, + .xCR = 0x24, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { + .type = IMX_MU_TYPE_GENERIC, + .tx = imx_mu_generic_tx, + .rx = imx_mu_generic_rx, + .xTR = {0x20, 0x24, 0x28, 0x2c}, + .xRR = {0x40, 0x44, 0x48, 0x4c}, + .xSR = 0x60, + .xCR = 0x64, +}; + static const struct of_device_id imx_mu_dt_ids[] = { { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
--
2.16.4
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