Thread (38 messages) 38 messages, 4 authors, 2020-02-24

RE: [PATCHv10 12/13] arm64: dts: lx2160a: Add PCIe controller DT nodes

From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Date: 2020-02-24 06:11:42
Also in: linux-devicetree, linux-pci, lkml 

Hi Shawn,


-----Original Message-----
From: Shawn Guo <shawnguo@kernel.org>
Sent: 2020年2月24日 9:28
To: Z.q. Hou <zhiqiang.hou@nxp.com>
Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
bhelgaas@google.com; robh+dt@kernel.org; andrew.murray@arm.com;
arnd@arndb.de; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
m.karthikeyan@mobiveil.co.in; Leo Li [off-list ref];
lorenzo.pieralisi@arm.com; catalin.marinas@arm.com;
will.deacon@arm.com; Mingkai Hu [off-list ref]; M.h. Lian
[off-list ref]; Xiaowei Bao [off-list ref]
Subject: Re: [PATCHv10 12/13] arm64: dts: lx2160a: Add PCIe controller DT
nodes

On Thu, Feb 13, 2020 at 12:06:43PM +0800, Zhiqiang Hou wrote:
quoted
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The LX2160A integrated 6 PCIe Gen4 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
V10:
 - No change

 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163
++++++++++++++++++
 1 file changed, 163 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index e5ee5591e52b..aee2810d91cc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1076,5 +1076,168 @@
 				};
 			};
 		};
+
+		pcie@3400000 {
The nodes should be sorted in unit-address.  That said, they should be
added after ata3: sata@3230000.
quoted
+			compatible = "fsl,lx2160a-pcie";
+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller
registers */
quoted
+			       0x80 0x00000000 0x0 0x00001000>; /* configuration
space */
quoted
+			reg-names = "csr_axi_slave", "config_axi_slave";
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER
interrupt */
quoted
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME
interrupt */
quoted
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
quoted
+			interrupt-names = "aer", "pme", "intr";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			apio-wins = <8>;
+			ppio-wins = <8>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
quoted
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 2 &gic 0 0 GIC_SPI 110
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 3 &gic 0 0 GIC_SPI 111
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 4 &gic 0 0 GIC_SPI 112
IRQ_TYPE_LEVEL_HIGH>;
quoted
+			status = "disabled";
+		};
+
+		pcie@3500000 {
+			compatible = "fsl,lx2160a-pcie";
+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller
registers */
quoted
+			       0x88 0x00000000 0x0 0x00001000>; /* configuration
space */
quoted
+			reg-names = "csr_axi_slave", "config_axi_slave";
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER
interrupt */
quoted
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME
interrupt */
quoted
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
quoted
+			interrupt-names = "aer", "pme", "intr";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			apio-wins = <8>;
+			ppio-wins = <8>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
quoted
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 2 &gic 0 0 GIC_SPI 115
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 3 &gic 0 0 GIC_SPI 116
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 4 &gic 0 0 GIC_SPI 117
IRQ_TYPE_LEVEL_HIGH>;
quoted
+			status = "disabled";
+		};
+
+		pcie@3600000 {
+			compatible = "fsl,lx2160a-pcie";
+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller
registers */
quoted
+			       0x90 0x00000000 0x0 0x00001000>; /* configuration
space */
quoted
+			reg-names = "csr_axi_slave", "config_axi_slave";
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER
interrupt */
quoted
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME
interrupt */
quoted
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
quoted
+			interrupt-names = "aer", "pme", "intr";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			apio-wins = <256>;
+			ppio-wins = <24>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
quoted
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 2 &gic 0 0 GIC_SPI 120
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 3 &gic 0 0 GIC_SPI 121
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 4 &gic 0 0 GIC_SPI 122
IRQ_TYPE_LEVEL_HIGH>;
quoted
+			status = "disabled";
+		};
+
+		pcie@3700000 {
+			compatible = "fsl,lx2160a-pcie";
+			reg = <0x00 0x03700000 0x0 0x00100000   /* controller
registers */
quoted
+			       0x98 0x00000000 0x0 0x00001000>; /* configuration
space */
quoted
+			reg-names = "csr_axi_slave", "config_axi_slave";
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER
interrupt */
quoted
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME
interrupt */
quoted
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
quoted
+			interrupt-names = "aer", "pme", "intr";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			apio-wins = <8>;
+			ppio-wins = <8>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
quoted
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 2 &gic 0 0 GIC_SPI 125
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 3 &gic 0 0 GIC_SPI 126
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 4 &gic 0 0 GIC_SPI 127
IRQ_TYPE_LEVEL_HIGH>;
quoted
+			status = "disabled";
+		};
+
+		pcie@3800000 {
+			compatible = "fsl,lx2160a-pcie";
+			reg = <0x00 0x03800000 0x0 0x00100000   /* controller
registers */
quoted
+			       0xa0 0x00000000 0x0 0x00001000>; /* configuration
space */
quoted
+			reg-names = "csr_axi_slave", "config_axi_slave";
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER
interrupt */
quoted
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME
interrupt */
quoted
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
quoted
+			interrupt-names = "aer", "pme", "intr";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			apio-wins = <256>;
+			ppio-wins = <24>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
quoted
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 2 &gic 0 0 GIC_SPI 130
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 3 &gic 0 0 GIC_SPI 131
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 4 &gic 0 0 GIC_SPI 132
IRQ_TYPE_LEVEL_HIGH>;
quoted
+			status = "disabled";
+		};
+
+		pcie@3900000 {
+			compatible = "fsl,lx2160a-pcie";
+			reg = <0x00 0x03900000 0x0 0x00100000   /* controller
registers */
quoted
+			       0xa8 0x00000000 0x0 0x00001000>; /* configuration
space */
quoted
+			reg-names = "csr_axi_slave", "config_axi_slave";
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER
interrupt */
quoted
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME
interrupt */
quoted
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /*
controller interrupt */
quoted
+			interrupt-names = "aer", "pme", "intr";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			apio-wins = <8>;
+			ppio-wins = <8>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0
0x40000000>; /* non-prefetchable memory */
quoted
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 2 &gic 0 0 GIC_SPI 105
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 3 &gic 0 0 GIC_SPI 106
IRQ_TYPE_LEVEL_HIGH>,
quoted
+					<0000 0 0 4 &gic 0 0 GIC_SPI 107
IRQ_TYPE_LEVEL_HIGH>;
quoted
+			status = "disabled";
+		};
+
Unnecessary newline.

I fixed them up and applied the patch.
Thanks a lot for your help!

Thanks,
Zhiqiang

Shawn
quoted
 	};
 };
--
2.17.1
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