Re: [Question] About handling PMU context loss in the deepest idle state where the core is powered down

[+Lorenzo]

On Thu, Jan 09, 2020 at 10:43:40AM +0800, Xiongfeng Wang wrote:

Sorry to bother you. It's just that we have come across some problems
about PMU recently.

No bother, and thanks for including the mailing list.

We are working on deep power state on CPU cores. In the deepest idle state, the core will be
powered down. In our implementation, the PMU and the core are in the same power domain,
so the PMU will also be powered down. But I didn't find where we saved the PMU context
in kernel before entering the deepest idle state.

Before we enter the system sleep state, we update the kernel PMU counter and stop the PMU
in 'cpu_pm_pmu_notify()'. But we didn't do that before we enter idle state.
I only find some system registers saving in 'psci_cpu_suspend_enter()->cpu_susend()->cpu_do_suspend()'

I'm not sure what you mean by "system sleep state", but if you're putting
the CPU into a state where register contents is lost, then I think you need
those PM notifiers to run. My understanding was that CPUidle took care of
this. Why is that not sufficient for you?

Do you have some suggestion about how we can handle this problem ?
Should we save and restore the PMU context before and after the deepest idle state . I don't know
if we can take care of the PMU  counters and interrupts properly by saving and restoring
the PMU registers.
Or we should update the kernel counter and stop the PMU, like what we did in system sleep situation.
Or we should let the firmware to handle the saving and restoring problem.

If the idle state is somehow autonomous (i.e. the kernel is not aware of
it), then I suppose firmware has to save/restore the register state that
is not otherwise preserved. However, I'd like to understand if this is
really what's happening and why CPUidle isn't just doing the right thing.

Thanks,

Will

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