[PATCH v7 5/5] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller
From: Hanjie Lin <hidden>
Date: 2020-01-20 02:58:38
Also in:
linux-amlogic, linux-devicetree, linux-usb
Subsystem:
arm/amlogic meson soc support, the rest · Maintainers:
Neil Armstrong, Kevin Hilman, Linus Torvalds
Enable USB2 PHY and DWC3 controller for Meson A1 SoC. Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <redacted> --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 6fdc0dd..3b7ca50 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi@@ -6,6 +6,9 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/meson-a1-power.h> +#include <dt-bindings/reset/amlogic,meson-a1-reset.h> +#include <dt-bindings/clock/a1-pll-clkc.h> +#include <dt-bindings/clock/a1-clkc.h> / { compatible = "amlogic,a1";
@@ -100,6 +103,17 @@ #power-domain-cells = <1>; status = "okay"; }; + + usb2_phy1: phy@40000 { + compatible = "amlogic,a1-usb2-phy"; + clocks = <&clkc_periphs CLKID_XTAL_USB_PHY>; + clock-names = "xtal"; + reg = <0x0 0x40000 0x0 0x2000>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; }; gic: interrupt-controller@ff901000 {
@@ -114,6 +128,35 @@ #interrupt-cells = <3>; #address-cells = <0>; }; + + usb: usb@ffe09000 { + status = "disabled"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc_periphs CLKID_USB_CTRL>, + <&clkc_periphs CLKID_USB_BUS>, + <&clkc_periphs CLKID_XTAL_USB_CTRL>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + + dr_mode = "host"; + + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + }; }; timer {
--
2.7.4
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