Thread (10 messages) 10 messages, 3 authors, 2020-01-16

RE: [PATCH V2 2/4] clk: imx: imx8mq: use imx8m_clk_hw_composite_core

From: Peng Fan <peng.fan@nxp.com>
Date: 2020-01-16 01:48:21
Also in: linux-clk, lkml

Subject: Re: [PATCH V2 2/4] clk: imx: imx8mq: use
imx8m_clk_hw_composite_core

On Tue, Jan 14, 2020 at 04:49:20PM +0000, Leonard Crestez wrote:
quoted
On 10.01.2020 09:17, Peng Fan wrote:
quoted
From: Peng Fan <peng.fan@nxp.com>

Use imx8m_clk_hw_composite_core to simplify code.

Reviewed-by: Abel Vesa <redacted>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
  drivers/clk/imx/clk-imx8mq.c | 19 +++++--------------
  1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c
b/drivers/clk/imx/clk-imx8mq.c index 4c0edca1a6d0..b031183ff427
100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -403,22 +403,13 @@ static int imx8mq_clocks_probe(struct
platform_device *pdev)

  	/* CORE */
  	hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
quoted
quoted
-	hws[IMX8MQ_CLK_M4_SRC] = imx_clk_hw_mux2("arm_m4_src", base
+ 0x8080, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels));
quoted
quoted
-	hws[IMX8MQ_CLK_VPU_SRC] = imx_clk_hw_mux2("vpu_src", base +
0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
quoted
quoted
-	hws[IMX8MQ_CLK_GPU_CORE_SRC] =
imx_clk_hw_mux2("gpu_core_src", base + 0x8180, 24, 3,
imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
quoted
quoted
-	hws[IMX8MQ_CLK_GPU_SHADER_SRC] =
imx_clk_hw_mux2("gpu_shader_src", base + 0x8200, 24, 3,
imx8mq_gpu_shader_sels,  ARRAY_SIZE(imx8mq_gpu_shader_sels));
quoted
quoted
-
  	hws[IMX8MQ_CLK_A53_CG] =
imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28,
CLK_IS_CRITICAL);
quoted
quoted
-	hws[IMX8MQ_CLK_M4_CG] = imx_clk_hw_gate3("arm_m4_cg",
"arm_m4_src", base + 0x8080, 28);
quoted
quoted
-	hws[IMX8MQ_CLK_VPU_CG] = imx_clk_hw_gate3("vpu_cg", "vpu_src",
base + 0x8100, 28);
quoted
quoted
-	hws[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_hw_gate3("gpu_core_cg",
"gpu_core_src", base + 0x8180, 28);
quoted
quoted
-	hws[IMX8MQ_CLK_GPU_SHADER_CG] =
imx_clk_hw_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
quoted
quoted
-
  	hws[IMX8MQ_CLK_A53_DIV] =
imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
quoted
quoted
-	hws[IMX8MQ_CLK_M4_DIV] = imx_clk_hw_divider2("arm_m4_div",
"arm_m4_cg", base + 0x8080, 0, 3);
quoted
quoted
-	hws[IMX8MQ_CLK_VPU_DIV] = imx_clk_hw_divider2("vpu_div",
"vpu_cg", base + 0x8100, 0, 3);
quoted
quoted
-	hws[IMX8MQ_CLK_GPU_CORE_DIV] =
imx_clk_hw_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
quoted
quoted
-	hws[IMX8MQ_CLK_GPU_SHADER_DIV] =
imx_clk_hw_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0,
3);
quoted
quoted
+
+	hws[IMX8MQ_CLK_M4_DIV] =
imx8m_clk_hw_composite_core("arm_m4_div", imx8mq_arm_m4_sels, base
+ 0x8080);
quoted
quoted
+	hws[IMX8MQ_CLK_VPU_DIV] =
imx8m_clk_hw_composite_core("vpu_div", imx8mq_vpu_sels, base +
0x8100);
quoted
quoted
+	hws[IMX8MQ_CLK_GPU_CORE_DIV] =
imx8m_clk_hw_composite_core("gpu_core_div", imx8mq_gpu_core_sels,
base + 0x8180);
quoted
quoted
+	hws[IMX8MQ_CLK_GPU_SHADER_DIV] =
+imx8m_clk_hw_composite("gpu_shader_div", imx8mq_gpu_shader_sels,
+base + 0x8200);

  	/* BUS */
  	hws[IMX8MQ_CLK_MAIN_AXI] =
imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels,
base + 0x8800);
Collapsing _SRC _CG into _DIV is an useful simplification but it
technically breaks DT compatibility rules.

Inside imx8mq.dtsi there are clock assignments for
IMX8MQ_CLK_GPU_CORE_SRC and IMX8MQ_CLK_GPU_SHADER_SRC
which no longer
quoted
exist so those assignments don't take effect.
We do not want to break existing DTBs for this case.  Patches dropped.
I'll send a v3 to address the issues. Sorry.

Thanks,
Peng.
Shawn
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