Hi Florian,

On Mon, 2019-12-30 at 11:05 -0800, Florian Fainelli wrote:

On 12/12/19 2:01 AM, Philipp Zabel wrote:

[...]

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+	reg = readl(base + BRCM_RESCAL_START);
+	writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
+	reg = readl(base + BRCM_RESCAL_START);
+	if (!(reg & BRCM_RESCAL_START_BIT)) {
+		dev_err(data->dev, "failed to start sata/pcie rescal\n");

Is this something that can actually happen?

Have not seen it happen but if we have bogus hardware, we would rather
get an informative log from the reset controller than a not so
informative one from the consumer drivers about e.g.: SATA or PCIe link
down (which could be for various other reasons). If you want this
demoted to a debug print, let me know.

Ok, that is not necessary. I was just surprised that you don't trust
register writes to work.

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+	reg = readl(base + BRCM_RESCAL_START);
+	writel(reg ^ BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);

Please use &= ~BRCM_RESCAL_START_BIT instead.

I think the idea was to avoid unconditionally clearing it, but based on
the documentation, I don't see this being harmful, Jim?

Unless the bit is self-clearing, I can't see how this XOR could ever set
the bit instead of clearing it.
And even if it would, I don't understand how that can be indented.
Wouldn't that restart the reset/calibration sequence?

The bit is not self clearing, but it can be cleared when the
reset/calibration procedure is successfully finished, so this seems to
do what it is intended for, in that, if you read the bit as 1, XOR would
let you clear it.

I'm with you so far ...

If you read it as 0, XOR would leave it cleared.

... but I don't understand this part. If BRCM_RESCAL_START is read as 0
at this point, we end up writing (0 ^ 1) == 1.

Would you want a comment above to explain that?

Yes, please.

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+	reg = readl(base + BRCM_RESCAL_START);
+	dev_dbg(data->dev, "sata/pcie rescal success\n");
+
+	return 0;
+}

This whole function looks a lot like it doesn't just deassert a reset
line, but actually issues a complete reset procedure of some kind. Do
you have some insight on what actually happens in the hardware when the
start bit is triggered? I suspect this should be implemented with the
.reset operation.

This hardware block is controlling the reset and calibration process of
the SATA/PCIe combo PHY analog front end, but is not technically part of
the PCIe or SATA PHY proper, it stands on its own, both functionally and
from a register space perspective. The motivation for modelling this as
a reset controller is that it does a reset (and a calibration) and this
is a shared reset line among 2/3 instances of another block. If you
think we should model this differently, please let us know.

Thank you for the explanation. I agree the "reset and calibration
sequence" property is close enough to a pure reset sequence to warrant
describing this as as reset controller.
The correct way would be to use the .reset callback though, if you can
have the drivers use reset_control_reset().

This should be doable, let me try to update the drivers accordingly. It
sounds a bit silly to have to have kind of knowledge pushed down to the
consumer drivers though...

There are cases where the abstraction doesn't fit perfectly, but usually
it is the consumer driver that knows best whether the hardware just
needs to be made responsive by deasserting the reset line, or whether
triggering a reset procedure is required to initialize some internal
state.

regards
Philipp


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