[PATCH 2/2] PCI: amlogic: Use PCIe pll gate when available
From: Remi Pommarel <hidden>
Date: 2019-12-08 20:55:30
Also in:
linux-amlogic, linux-clk, linux-pci, lkml
Subsystem:
pci native host bridge and endpoint drivers, pci subsystem, pcie driver for amlogic meson, the rest · Maintainers:
Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Yue Wang, Linus Torvalds
In order to get PCIe working reliably on some AXG platforms, PCIe pll cml needs to be enabled. This is done by using the PCIE_PLL_CML_ENABLE clock gate. This clock gate is optional, so do not fail if it is missing in the devicetree. Signed-off-by: Remi Pommarel <redacted> --- drivers/pci/controller/dwc/pci-meson.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 3772b02a5c55..32b70ea9a426 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c@@ -89,6 +89,7 @@ struct meson_pcie_clk_res { struct clk *mipi_gate; struct clk *port_clk; struct clk *general_clk; + struct clk *pll_cml_gate; }; struct meson_pcie_rc_reset {
@@ -300,6 +301,10 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp) if (IS_ERR(res->clk)) return PTR_ERR(res->clk); + res->pll_cml_gate = meson_pcie_probe_clock(dev, "pll_cml_en", 0); + if (IS_ERR(res->pll_cml_gate)) + res->pll_cml_gate = NULL; + return 0; }
--
2.24.0
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