On 19-11-12 13:43:35, Leonard Crestez wrote:

On 12.11.2019 13:18, Abel Vesa wrote:

quoted

On 19-11-09 00:39:51, Leonard Crestez wrote:

quoted

These clocks are only modified as part of DRAM frequency switches during
which DRAM itself is briefly inaccessible. The switch is performed with
a SMC call to by TF-A which runs from a SRAM area; upon returning to
linux several clocks bits are modified and we need to update them.

For rate bits an easy solution is to just mark with
CLK_GET_RATE_NOCACHE so that new rates are always read back from
registers.

Signed-off-by: Leonard Crestez <redacted>
---
  drivers/clk/imx/clk-imx8mm.c | 11 +++++++++--
  drivers/clk/imx/clk-imx8mn.c | 12 ++++++++++--
  drivers/clk/imx/clk-imx8mq.c | 15 +++++++++++----
  3 files changed, 30 insertions(+), 8 deletions(-)

quoted

quoted

--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c

@@ -428,12 +428,20 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
  	clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
  	clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
  	clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
  	clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
  	clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
-	clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
-	clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
+
+	/*
+	 * DRAM clocks are manipulated from TF-A outside clock framework.
+	 * Mark with GET_RATE_NOCACHE to always read div value from hardware
+	 */
+	clks[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000,
+			CLK_GET_RATE_NOCACHE);
+	clks[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080,
+			CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);

nitpick: I think it looks better if we stick to one line each clock.
I know it's against the 80 chars rule, but at least is consistent.

Yes, there are longer lines in the imx8m* files anyway.

If I fix this (in all instances) can I also add a "reviewed-by"?

Sorry, I forgot to add the line.

For all the clock related changes:

Reviewed-by: Abel Vesa <redacted>

--
Regards,
Leonard

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