[PATCH v3 8/8] ARM: realtek: Enable RTD1195 arch timer
From: Andreas Färber <afaerber@suse.de>
Date: 2019-11-17 07:21:27
Also in:
lkml
Subsystem:
arm port, arm/realtek architecture, the rest · Maintainers:
Russell King, James Tai, Yu-Chun Lin, Linus Torvalds
Without this magic write the timer doesn't work and boot gets stuck. Signed-off-by: Andreas Färber <afaerber@suse.de> --- What is the name of the register 0xff018000? Is 0x1 a BIT(0) write, or how are the register bits defined? Is this a reset or a clock gate? How should we model it in DT? v2 -> v3: Unchanged v2: New arch/arm/mach-realtek/rtd1195.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c
index b31a4066be87..0532379c74f5 100644
--- a/arch/arm/mach-realtek/rtd1195.c
+++ b/arch/arm/mach-realtek/rtd1195.c@@ -5,6 +5,9 @@ * Copyright (c) 2017-2019 Andreas Färber */ +#include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/io.h> #include <linux/memblock.h> #include <asm/mach/arch.h>
@@ -24,6 +27,18 @@ static void __init rtd1195_reserve(void) rtd1195_memblock_remove(0x18100000, 0x01000000); } +static void __init rtd1195_init_time(void) +{ + void __iomem *base; + + base = ioremap(0xff018000, 4); + writel(0x1, base); + iounmap(base); + + of_clk_init(NULL); + timer_probe(); +} + static const char *const rtd1195_dt_compat[] __initconst = { "realtek,rtd1195", NULL
@@ -31,6 +46,7 @@ static const char *const rtd1195_dt_compat[] __initconst = { DT_MACHINE_START(rtd1195, "Realtek RTD1195") .dt_compat = rtd1195_dt_compat, + .init_time = rtd1195_init_time, .reserve = rtd1195_reserve, .l2c_aux_val = 0x0, .l2c_aux_mask = ~0x0,
--
2.16.4
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