[PATCH v6 5/7] arm64: dts: bitmain: Source common clock for UART controllers
From: Manivannan Sadhasivam <hidden>
Date: 2019-10-26 11:03:43
Also in:
linux-clk, linux-devicetree, lkml
Subsystem:
arm/bitmain architecture, the rest · Maintainers:
Manivannan Sadhasivam, Linus Torvalds
Remove fixed clock and source common clock for UART controllers. Signed-off-by: Manivannan Sadhasivam <redacted> --- arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts | 9 --------- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
index 3e8c70778e24..7a2c7f9c2660 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
+++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts@@ -49,12 +49,6 @@ reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <500000000>; - #clock-cells = <0>; - }; - soc { gpio0: gpio@50027000 { porta: gpio-controller@0 {
@@ -173,21 +167,18 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &uart2 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_default>; };
diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi
index 8471662413da..fa6e6905f588 100644
--- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi
+++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi@@ -174,6 +174,9 @@ uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>;
@@ -184,6 +187,9 @@ uart1: serial@5801A000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801a000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>;
@@ -194,6 +200,9 @@ uart2: serial@5801C000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801c000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>;
@@ -204,6 +213,9 @@ uart3: serial@5801E000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801e000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>;
--
2.17.1
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