Re: [PATCH v3 1/5] clk: rockchip: Add supprot to limit input rate for fractional divider

diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index 3a501896b280..6c2f53dc73b6 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c

@@ -13,6 +13,7 @@
 #include "clk.h"
 
 #define PX30_GRF_SOC_STATUS0           0x480
+#define PX30_FRAC_MAX_PRATE            600000000
 
 enum px30_plls {
        apll, dpll, cpll, npll, apll_b_h, apll_b_l,

@@ -420,7 +421,7 @@ enum px30_pmu_plls {
        COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
                        PX30_CLKSEL_CON(6), 0,
                        PX30_CLKGATE_CON(2), 3, GFLAGS,
-                       &px30_dclk_vopb_fracmux),
+                       &px30_dclk_vopb_fracmux, 0),
        GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
                        PX30_CLKGATE_CON(2), 4, GFLAGS),
        COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,

@@ -429,7 +430,7 @@ enum px30_pmu_plls {
        COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
                        PX30_CLKSEL_CON(9), 0,
                        PX30_CLKGATE_CON(2), 7, GFLAGS,
-                       &px30_dclk_vopl_fracmux),
+                       &px30_dclk_vopl_fracmux, 0),
        GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
                        PX30_CLKGATE_CON(2), 8, GFLAGS),
 

@@ -555,7 +556,7 @@ enum px30_pmu_plls {
        COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,

                        PX30_CLKSEL_CON(27), 0,
                        PX30_CLKGATE_CON(9), 10, GFLAGS,
-                       &px30_pdm_fracmux),
+                       &px30_pdm_fracmux, PX30_FRAC_MAX_PRATE),
        GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
                        PX30_CLKGATE_CON(9), 11, GFLAGS),
 

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..bda5d50c5319 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c

@@ -13,6 +13,12 @@
 #include <dt-bindings/clock/rk3399-cru.h>
 #include "clk.h"
 
+#define RK3399_I2S_FRAC_MAX_PRATE       800000000
+#define RK3399_UART_FRAC_MAX_PRATE     800000000
+#define RK3399_SPDIF_FRAC_MAX_PRATE    600000000
+#define RK3399_VOP_FRAC_MAX_PRATE      600000000
+#define RK3399_WIFI_FRAC_MAX_PRATE     600000000

+
 enum rk3399_plls {
        lpll, bpll, dpll, cpll, gpll, npll, vpll,
 };

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..fac5a4a3f5c3 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c

@@ -184,12 +184,26 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
        unsigned long p_rate, p_parent_rate;
        struct clk_hw *p_parent;
        unsigned long scale;
+       u32 div;

+                              clk_hw_get_name(hw), *parent_rate, rate);
+                       *m = 0;
+                       *n = 1;
+                       return;
+               }
        }
 
        /*

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2ae7604783dd..30993c0630a3 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h

@@ -624,6 +624,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
  * @mwidth:    width of the numerator bit field
  * @nshift:    shift to the denominator bit field
  * @nwidth:    width of the denominator bit field
+ * @max_parent:        the maximum frequency of fractional divider parent clock

  * @lock:      register lock
  *
  * Clock with adjustable fractional divider affecting its output frequency.

@@ -647,6 +648,7 @@ struct clk_fractional_divider {
        u8              nwidth;
        u32             nmask;
        u8              flags;
+       unsigned long   max_prate;