[PATCH v3 13/15] drm/mxsfb: Clear OUTSTANDING_REQS bits
From: Robert Chiras <robert.chiras@nxp.com>
Date: 2019-08-21 10:16:32
Also in:
dri-devel, linux-devicetree, lkml
Subsystem:
drm drivers, drm drivers and misc gpu patches, mxsfb drm driver, the rest · Maintainers:
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Marek Vasut, Stefan Agner, Linus Torvalds
Bit 21 can alter the CTRL2_OUTSTANDING_REQS value right after the eLCDIF is enabled, since it comes up with default value of 1 (this behaviour has been seen on some imx8 platforms). In order to fix this, clear CTRL2_OUTSTANDING_REQS bits before setting its value. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> --- drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index e727f5e..a12f53d 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c@@ -225,6 +225,13 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) clk_prepare_enable(mxsfb->clk); if (mxsfb->devdata->ipversion >= 4) { + /* + * On some platforms, bit 21 is defaulted to 1, which may alter + * the below setting. So, to make sure we have the right setting + * clear all the bits for CTRL2_OUTSTANDING_REQS. + */ + writel(CTRL2_OUTSTANDING_REQS(0x7), + mxsfb->base + LCDC_V4_CTRL2 + REG_CLR); writel(CTRL2_OUTSTANDING_REQS(REQ_16), mxsfb->base + LCDC_V4_CTRL2 + REG_SET); /* Assert LCD Reset bit */
--
2.7.4
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