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+====================================================
+Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
+====================================================
+
+There are no performance counters inside the DRAM controller, so performance
+signals are brought out to the edge of the controller where a set of 4 x 32 bit
+counters is implemented. This is controlled by the Performance log on parameter
+which causes a large number of PERF signals to be generated.
+
+Selection of the value for each counter is done via the config registiers. There
+is one register for each counter. Counter 0 is special in that it always counts
+“time” and when expired causes a lock on itself and the other counters and an
+interrupt ie enable of counter 0 is a global function.
+
+The "format" directory describes format of the config (event ID) and config1
+(AXI ID filter) fields of the perf_event_attr structure, see /sys/bus/event_source/
+devices/imx8_ddr0/format/. The "events" directory describes the events types
+hardware supported that can be used with perf tool, see /sys/bus/event_source/
+devices/imx8_ddr0/events/.
+
+AXI filtering is used by CSV modes 0x41 (axi-id-read event) and 0x42 (axi-id-write
+event) to count reads or writes matching filter setting. Read and write AXI ID
+filter must have the same value if you want to specify them at the same time as
+this filter is shared between counters.
+
+Example for perf tool use::
+
+        perf stat -e imx8_ddr0/cycles/ sleep 1
+        perf stat -e imx8_ddr0/read/,imx8_ddr0/write/ sleep 1
+        perf stat -e imx8_ddr0/axi-id-read,axi_id=0xMMMMDDDD/,imx8_ddr0/axi-id-write,axi_id=0xMMMMDDDD/ sleep 1