Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support
From: Florian Fainelli <f.fainelli@gmail.com>
Date: 2019-07-18 18:05:34
On 7/18/19 10:53 AM, Stefan Wahren wrote:
Hi Mark, Am 18.07.19 um 14:42 schrieb Mark Brown:quoted
On Wed, Jul 17, 2019 at 11:16:01PM +0200, Stefan Wahren wrote:quoted
+ /* check if we got interrupt enabled */ + if (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR)) + return IRQ_NONE; +Is that checking if the interrupt is enabled or if it is asserted?the BCM2835 doesn't provide a SPI register, which shows that the interrupt has been asserted. So i think, Martin tried to adapt the workaround from spi-bcm2835-aux which has the same problem.
I was about to submit a change to address that since we also have that shared interrupt on BCM7211: https://github.com/ffainelli/linux/commit/15d96d82bd42991dc71369128131312d5338f65c Martin's patch is more efficient in terms of amount of register accesses, but I am bit worried (based on the register description) that the INTR bit is only asserted with the read FIFO crossing a certain condition and that a TX only transfer may not be captured by that condition. Maybe we can just check spi_controller::idling to determine if that specific instance generated an interrupt? -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel