On Tue, Jul 02, 2019 at 12:30:14AM +0530, Jagan Teki wrote:

On Tue, Jun 25, 2019 at 8:07 PM Maxime Ripard [off-list ref] wrote:

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BSP has tcon_div and dsi_div. dsi_div is dynamic which depends on
bpp/lanes and it indeed depends on PLL computation (not tcon_div),
anyway I have explained again on this initial link you mentioned.
Please have a look and get back.

I'll have a look, thanks.

I've given your patches a try on my setup though, and this patch
breaks it with vblank timeouts and some horizontal lines that looks
like what should be displayed, but blinking and on the right of the
display. The previous ones are fine though.

Would you please send me the link of panel driver.

It's drivers/gpu/drm/panel/panel-ronbo-rb070d30.c

Look like this panel work even w/o any vendor sequence. it's similar
to the 4-lane panel I have with RGB888, so the dclk div is 6, is it
working with this divider?

It works with 4, it doesn't work with 6.

Can be the pixel clock with associated timings can make this diff.
Would you send me the pixel clock, pll_rate and timings this panel
used it from BSP?

This board never had an Allwinner BSP

Running on BSP would help to understand some clue, anyway would you
send me the the value PLL_MIPI register (devme 0x1c20040) on this
board. I'm trying to understand how it value in your case.

I'm sorry, but I'm not going to port a whole BSP on that board,
especially for something I haven't been convinced it's the right fix.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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