Re: [PATCH 1/2] Documentation: perf: Update documentation for ThunderX2 PMU uncore driver
From: Will Deacon <will@kernel.org>
Date: 2019-06-27 10:01:26
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On Fri, Jun 14, 2019 at 05:42:45PM +0000, Ganapatrao Kulkarni wrote:
quoted hunk ↗ jump to hunk
From: Ganapatrao Kulkarni <redacted> Add documentation for Cavium Coherent Processor Interconnect (CCPI2) PMU. Signed-off-by: Ganapatrao Kulkarni <redacted> --- Documentation/perf/thunderx2-pmu.txt | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt index dffc57143736..62243230abc3 100644 --- a/Documentation/perf/thunderx2-pmu.txt +++ b/Documentation/perf/thunderx2-pmu.txt@@ -2,24 +2,26 @@ Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) ============================================================= The ThunderX2 SoC PMU consists of independent, system-wide, per-socket -PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC). +PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and +Cavium Coherent Processor Interconnect (CCPI2). The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles. Events are counted for the default channel (i.e. channel 0) and prorated to the total number of channels/tiles. -The DMC and L3C support up to 4 counters. Counters are independently -programmable and can be started and stopped individually. Each counter -can be set to a different event. Counters are 32-bit and do not support -an overflow interrupt; they are read every 2 seconds. +The DMC, L3C support up to 4 counters and CCPI2 support up to 8 counters.
The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8 counters.
+Counters are independently programmable and can be started and stopped +individually. Each counter can be set to a different event. DMC and L3C +Counters are 32-bit and do not support an overflow interrupt; they are read
Counters -> counters
+every 2 seconds. CCPI2 counters are 64-bit.
Assuming CCPI2 also doesn't support an overflow interrupt, I'd reword these two sentences as: None of the counters support an overflow interrupt and therefore sampling events are unsupported. The DMC and L3C counters are 32-bit and read every 2 seconds. The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
PMU UNCORE (perf) driver: The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and -L3C devices. Each PMU can be used to count up to 4 events -simultaneously. The PMUs provide a description of their available events -and configuration options under sysfs, see -/sys/devices/uncore_<l3c_S/dmc_S/>; S is the socket id. +L3C devices. Each PMU can be used to count up to 4(DMC/L3C) or up to 8
Space between 4 and ( Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel