Re: [PATCH v7 10/21] iommu/mediatek: Move reset_axi into plat_data
From: Matthias Brugger <matthias.bgg@gmail.com>
Date: 2019-06-17 10:19:45
Also in:
linux-devicetree, linux-iommu, linux-mediatek, lkml
On 10/06/2019 14:17, Yong Wu wrote:
In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is REG_MMU_CTRL in the other SoCs, and the bits meaning is completely different with the REG_MMU_STANDARD_AXI_MODE. This patch moves this property to plat_data, it's also a preparing patch for mt8183. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Nicolas Boichat <redacted> Reviewed-by: Evan Green <redacted>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
quoted hunk ↗ jump to hunk
--- drivers/iommu/mtk_iommu.c | 4 ++-- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index d38dfa2..8ac7034 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c@@ -557,8 +557,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); - /* It's MISC control register whose default value is ok except mt8173.*/ - if (data->plat_data->m4u_plat == M4U_MT8173) + if (data->plat_data->reset_axi) writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,@@ -752,6 +751,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) .m4u_plat = M4U_MT8173, .has_4gb_mode = true, .has_bclk = true, + .reset_axi = true, .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ };diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 61fd5d6..55d73c1 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h@@ -46,7 +46,7 @@ struct mtk_iommu_plat_data { /* HW will use the EMI clock if there isn't the "bclk". */ bool has_bclk; - + bool reset_axi; unsigned char larbid_remap[MTK_LARB_NR_MAX]; };
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