[PATCH] arm64: cache: Update cache_line_size for HiSilicon certain platform

For HiSilicon's certain platform, like Kunpeng920 server SoC, it uses the
tsv110 CPUs whose L1 cache line size is 64-Byte, while the cache line size
of L3C is 128-Byte.
cache_line_size is used mostly for IO device drivers, so we shall correct
the right value and the device drivers can match it accurately to get good
performance.

When test mlx5 with Kunpeng920 SoC, ib_send_bw is run under the condition
that the length of the packet is 4-Byte and only one queue and cpu core:
Without this patch: 1.67 Mpps
with this patch   : 2.40 Mpps

Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: John Garry <redacted>
Cc: Zhenfa Qiu <redacted>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <redacted>
Reported-by: Zhenfa Qiu <redacted>
Signed-off-by: Shaokun Zhang <redacted>
---
 arch/arm64/include/asm/cache.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 926434f413fa..0f7d9581e0b9 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h

@@ -93,7 +93,12 @@ static inline u32 cache_type_cwg(void)
 
 static inline int cache_line_size(void)
 {
-	u32 cwg = cache_type_cwg();
+	u32 cwg;
+
+	if (read_cpuid_part_number() == HISI_CPU_PART_TSV110)
+		return ARCH_DMA_MINALIGN;
+
+	cwg = cache_type_cwg();
 	return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
 }
 

-- 
2.7.4


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