Re: [linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected

On Wed, Feb 06, 2019 at 10:16:08AM +0100, Maxime Ripard wrote:

On Tue, Feb 05, 2019 at 09:49:17AM -0800, Vasily Khoruzhick wrote:

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On Tue, Feb 5, 2019 at 7:42 AM Maxime Ripard [off-list ref] wrote:

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On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote:

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On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng [off-list ref] wrote:

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IIRC, from the previous discussion, HDMI had a tolerancy requirement
in the standard. Do you know if there's such a thing for eDP? That
would solve the issue for all the eDP displays at once.

I don't have access to eDP standard - vesa.org says it's available to
members only.

Try out to grab an old version?

I remember 1.0 is open.

I can't find anything regarding dot clock tolerance in DisplayPort
specification.

I guess since the DP is a VESA spec, it's probably .5%, just like on
the EDID (well, CVT).

Unfortunately that's not enough for Pinebook. It needs 1% for 768p
panel.

And that mode is stored in the EDID as a standard (or established)
timing, or a detailed timing?

If the latter, then it should also provide the tolerancies as part of
the panel timing description.

The simple-panel driver can, in addition to a struct drm_display_mode
take a struct display_timings to specify the modes. These allow to
define <minimum, typical, maximum> triplets for each parameter, which
are usually found in panel datasheets.

Of course that's not going to help you much if all you have is EDID and
if that doesn't provide tolerances.

Thierry

If the former, then what would be the advertised pixel clock and the
one we can compute? Maybe we have a bug somewhere.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com