Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected

于 2019年2月5日 GMT+08:00 上午12:26:43, Vasily Khoruzhick [off-list ref] 写到:

On Mon, Feb 4, 2019 at 6:20 AM Maxime Ripard
[off-list ref] wrote:

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Hi,

On Sun, Feb 03, 2019 at 10:54:55AM -0800, Vasily Khoruzhick wrote:

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Clock rate check that was added in commit bb43d40d7c83 ("drm/sun4i:

rgb:

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Validate the clock rate") prevents some panel and bridges from

working with

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sun4i driver.

Unfortunately, dotclock frequency for some modes are not achievable

on

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sunxi hardware, and there's a slight deviation in rate returned by
clk_round_rate(), so they fail this check.

Experiments show that panels and bridges work fine with this slight
deviation, e.g. Pinebook that uses ANX6345 bridge with 768p eDP

panel

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requests 73 MHz, gets 72.296MHz instead (0.96% difference) and

works just

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fine.

This patch adds a 1% tolerence to the dot clock check when bridge

is

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connected.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

I'm not sure we want to make exceptions for all the hardware
combination we face, but we should go for something more generic (and
easier to maintain instead).

IIRC, from the previous discussion, HDMI had a tolerancy requirement
in the standard. Do you know if there's such a thing for eDP? That
would solve the issue for all the eDP displays at once.

I don't have access to eDP standard - vesa.org says it's available to
members only.

Try out to grab an old version?

I remember 1.0 is open.

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Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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