Thread (9 messages) 9 messages, 3 authors, 2019-02-26

Re: [PATCH v2] clk: imx: Refactor entire sccg pll clk

From: Stephen Boyd <sboyd@kernel.org>
Date: 2019-02-25 17:23:17
Also in: linux-clk, lkml

Quoting Abel Vesa (2019-02-23 02:58:14)
On 19-02-22 09:46:23, Stephen Boyd wrote:
quoted
Quoting Abel Vesa (2019-02-22 09:07:32)
quoted
Make the entire combination of plls to be one single clock. The parents used
for bypasses are specified each as an index in the parents list.
The determine_rate does a lookup throughout all the possible combinations
for all the divs and returns the best possible 'setup' which in turn is used
by set_rate later to set up all the divs and bypasses.

Signed-off-by: Abel Vesa <redacted>
Tested-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
I suspect these tested by and acked tags should have been dropped,
unless you discussed and tested off-list?
Oups, I forgot to drop them.
Ok. Can Lucas re-test?


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