Re: [PATCH v2 1/1] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Matthias Brugger <matthias.bgg@gmail.com>
Date: 2019-02-14 09:19:02
Also in:
dmaengine, linux-devicetree, linux-mediatek, lkml
On 14/02/2019 08:54, shun-chih.yu@mediatek.com wrote:
quoted hunk ↗ jump to hunk
From: Shun-Chih Yu <redacted> Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6765 SoC or other similar Mediatek SoCs. Signed-off-by: Shun-Chih Yu <redacted> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sean Wang <sean.wang@kernel.org> --- .../devicetree/bindings/dma/mtk-cqdma.txt | 31 ++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txtdiff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt new file mode 100644 index 0000000..fb12927 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt@@ -0,0 +1,31 @@ +MediaTek Command-Queue DMA Controller +================================== + +Required properties: + +- compatible: Must be "mediatek,mt6765-cqdma" for MT6765. +- reg: Should contain the base address and length for each channel. +- interrupts: Should contain references to the interrupts for each channel. +- clocks: Should be the clock specifiers corresponding to the entry in + clock-names property. +- clock-names: Should contain "cqdma" entries.
entries -> entry. There is only one clock
+- dma-channels: The number of DMA channels supported by the controller. +- dma-requests: The number of DMA request supported by the controller.
The driver handles these as optional and uses MTK_CQDMA_NR_VCHANS and MTK_CQDMA_NR_PCHANS in case the property is not present.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+ cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;Does this mean that you have to resources at base = 0x0 with different length? Regards, Matthias
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_IFR_CQ_DMA>; + clock-names = "cqdma"; + dma-channels = <2>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +DMA clients must use the format described in dma/dma.txt file.
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