On Fri, Nov 30, 2018 at 07:05:06PM +0000, Robin Murphy wrote:

On 05/11/2018 12:19, Christoph Hellwig wrote:

quoted

The dma remap code only really makes sense for not cache coherent
architectures,

And coherent ones with highmem, presumably? That can at least be the case 
on 32-bit Arm, where coherent LPAE systems do exist (e.g. Calxeda Midway).

Ok, I've updated the commit log.

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