[PATCH v5 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller
From: Yogesh Narayan Gaur <hidden>
Date: 2018-11-16 11:14:10
Also in:
linux-devicetree, linux-spi, lkml
Subsystem:
open firmware and flattened device tree bindings, spi subsystem, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Mark Brown, Linus Torvalds
Add binding file for NXP FlexSPI controller Signed-off-by: Yogesh Gaur <redacted> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes for v5: - None Changes for v4: - Incorporated Rob review comments. Changes for v3: - Removed node property 'big-endian'. Changes for v2: - Incorporated Rob review comments. .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
new file mode 100644
index 0000000..2cd67eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt@@ -0,0 +1,39 @@ +* NXP Flex Serial Peripheral Interface (FSPI) + +Required properties: + - compatible : Should be "nxp,lx2160a-fspi" + - reg : First contains the register location and length, + Second contains the memory mapping address and length + - reg-names : Should contain the resource reg names: + - fspi_base: configuration register address space + - fspi_mmap: memory mapped address space + - interrupts : Should contain the interrupt for the device + +Required SPI slave node properties: + - reg : There are two buses (A and B) with two chip selects each. + This encodes to which bus and CS the flash is connected: + - <0>: Bus A, CS 0 + - <1>: Bus A, CS 1 + - <2>: Bus B, CS 0 + - <3>: Bus B, CS 1 + +Example showing the usage of two SPI NOR slave devices on bus A: + +fspi0: spi at 20c0000 { + compatible = "nxp,lx2160a-fspi"; + reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <0 25 0x4>; /* Level high type */ + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + + mt35xu512aba0: flash at 0 { + reg = <0>; + .... + }; + + mt35xu512aba1: flash at 1 { + reg = <1>; + .... + }; +};
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2.7.4