[PATCH v8 05/12] ARM: dts: aspeed: peci: Add PECI node
From: Jae Hyun Yoo <hidden>
Date: 2018-09-18 21:52:24
Also in:
linux-aspeed, linux-devicetree, linux-doc, linux-hwmon, lkml, openbmc
Subsystem:
the rest · Maintainer:
Linus Torvalds
This commit adds PECI bus/adapter node of AST24xx/AST25xx into aspeed-g4 and aspeed-g5. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <redacted> Cc: Jason M Biils <redacted> Cc: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Jae Hyun Yoo <redacted> Reviewed-by: Haiyue Wang <redacted> Reviewed-by: James Feist <redacted> Reviewed-by: Vernon Mauery <redacted> --- arch/arm/boot/dts/aspeed-g4.dtsi | 26 ++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b23a983f95a5..ba31b2f0e0d8 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi@@ -29,6 +29,7 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + peci0 = &peci0; }; cpus {
@@ -317,6 +318,13 @@ }; }; + peci: bus at 1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + }; + uart2: serial at 1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>;
@@ -360,6 +368,24 @@ }; }; +&peci { + peci0: peci-bus at 0 { + compatible = "aspeed,ast2400-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + msg-timing = <1>; + addr-timing = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; +}; + &i2c { i2c_ic: interrupt-controller at 0 { #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 87fdc146ff52..c93ab96131e6 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi@@ -29,6 +29,7 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + peci0 = &peci0; }; cpus {
@@ -377,6 +378,13 @@ }; }; + peci: bus at 1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + }; + uart2: serial at 1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>;
@@ -420,6 +428,24 @@ }; }; +&peci { + peci0: peci-bus at 0 { + compatible = "aspeed,ast2500-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + msg-timing = <1>; + addr-timing = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; +}; + &i2c { i2c_ic: interrupt-controller at 0 { #interrupt-cells = <1>;
--
2.18.0