Thread (5 messages) 5 messages, 3 authors, 2018-09-05

[PATCH] clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks

From: icenowy@aosc.io (Icenowy Zheng)
Date: 2018-08-27 23:20:50
Also in: linux-clk, lkml


? 2018?8?28? GMT+08:00 ??4:23:54, Stephen Boyd [off-list ref] ??:
Quoting Icenowy Zheng (2018-08-20 06:40:13)
quoted
On the H6, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.

To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.

This patch adds the post-dividers to the MMC clocks, following the
approach on A64.

Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6
CCU")

This commit doesn't exist. Did you mean:

524353ea48

instead?
Yes, it is.

Thanks!
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