HI Martin:
 thanks for your suggestion

On 07/10/18 06:02, Martin Blumenstingl wrote:

Hi Yixun,

On Thu, Jul 5, 2018 at 4:53 AM Yixun Lan [off-list ref] wrote:

quoted

HI Neil

On 07/04/18 22:57, Neil Armstrong wrote:

quoted

Hi Yixun,

On 05/07/2018 00:45, Yixun Lan wrote:

quoted

This patch series try to add pinctrl driver support for
the Meson-G12A SoC.

Thanks for submitting these patches.

Can you explicit this patchset with more details on the G12A SoC family ?
It's relationship with AXG and the differences in term of pinmuxing with the other SoC families ?

I thought this was already discussed while we doing pinctrl driver for
Meson-AXG SoC.

Anyway, here it is:

Starting from Meson-AXG SoC, the pinctrl controller block using 4
continues bit to specific pin mux function, while comparing to old
generation SoC which kind of using various length bits for the pin mux
definition. The new design would greatly simplify the software model..

for detail example, one 32bit register can describe 8 pins, and each of
them has 0-7 value to set, start from value 0 to 7.

partition the register into 8 parts:
bit[3:0]
bit[7:4]
bit[11:8]
bit[15:12]
bit[19:16]
bit[23:20]
bit[27:24]
bit[31:28]


for each value:
value == 0, means the pin is GPIO
value = {1, 2, ... 7 } is one of specific PIN function

OK, so AXG and G12A use the same register layout -> thus the same
pinmux ops are re-used

Yes

quoted

I could put this info into cover-letter or commit message?

if you have to resend this series anyways then it would be great if
you could add it to the commit description

sure

quoted

quoted

Why is there a GPIOE bank within the AO controller ?

It actually sit in the AO domain, although it's sounds strange from the
naming..

I'm not sure if it's good idea to append a AO suffix? since the
documentation just use the plain GPIOE

I am fine with plain GPIOE if that's what your internal documentation uses
it would be great if you could add a comment (or at least a note in
the commit message) indicating that this is how the hardware is
designed (initially I thought this was a bug since I have no
documentation for the G12A chipset)

I can add a comment

Regards
Martin

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