[PATCH v3 15/17] arm64: dts: marvell: add AP806 SEI subnode
From: miquel.raynal@bootlin.com (Miquel Raynal)
Date: 2018-06-22 15:14:30
Also in:
linux-devicetree
Subsystem:
arm/marvell kirkwood and armada 370, 375, 38x, 39x, xp, 3700, 7k/8k, cn9130 soc support, the rest · Maintainers:
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Linus Torvalds
Add the System Error Interrupt node, representing an IRQ chip which is part of the GIC. The SEI node has two subnodes, one for each interrupt domain: wired (from the AP) and not-wired (MSIs from the CPs). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 176e38d54872..4f2a704615b0 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi@@ -124,6 +124,17 @@ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; + sei: interrupt-controller at 3f0200 { + compatible = "marvell,armada-8k-sei"; + reg = <0x3f0200 0x40>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + marvell,sei-ap-ranges = <0 21>; + marvell,sei-cp-ranges = <21 43>; + #interrupt-cells = <1>; + interrupt-controller; + msi-controller; + }; + xor at 400000 { compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x400000 0x1000>,
--
2.14.1