Thread (19 messages) 19 messages, 4 authors, 2018-06-22

[PATCH V2 3/4] dt-bindings: arm: fsl: add scu binding doc

From: s.hauer@pengutronix.de (Sascha Hauer)
Date: 2018-06-21 07:37:28
Also in: linux-devicetree

On Thu, Jun 21, 2018 at 03:38:30AM +0000, A.s. Dong wrote:
Hi Rob,
quoted
-----Original Message-----
From: Rob Herring [mailto:robh at kernel.org]
Sent: Thursday, June 21, 2018 3:45 AM
To: A.s. Dong <aisheng.dong@nxp.com>
Cc: linux-arm-kernel at lists.infradead.org; dongas86 at gmail.com;
kernel at pengutronix.de; shawnguo at kernel.org; Fabio Estevam
[off-list ref]; dl-linux-imx [off-list ref]; Mark
Rutland [off-list ref]; devicetree at vger.kernel.org
Subject: Re: [PATCH V2 3/4] dt-bindings: arm: fsl: add scu binding doc

On Sun, Jun 17, 2018 at 08:49:48PM +0800, Dong Aisheng wrote:
quoted
The System Controller Firmware (SCFW) is a low-level system function
which runs on a dedicated Cortex-M core to provide power, clock, and
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
(QM, QP), and i.MX8QX (QXP, DX).

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <redacted>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree at vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * remove status
 * changed to mu1
---
 .../devicetree/bindings/arm/freescale/fsl,scu.txt  | 38
++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

diff --git
a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
new file mode 100644
index 0000000..9b7c9fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -0,0 +1,38 @@
+NXP i.MX System Controller Firmware (SCFW)
+--------------------------------------------------------------------
+
+The System Controller Firmware (SCFW) is a low-level system function
+which runs on a dedicated Cortex-M core to provide power, clock, and
+resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
+(QM, QP), and i.MX8QX (QXP, DX).
+
+The AP communicates with the SC using a multi-ported MU module found
+in the LSIO subsystem. The current definition of this MU module
+provides
+5 remote AP connections to the SC to support up to 5 execution
+environments (TZ, HV, standard Linux, etc.). The SC side of this MU
+module interfaces with the LSIO DSC IP bus. The SC firmware will
+communicate with this MU using the MSI bus.
+
+System Controller Device Node:
+=============================
+
+Required properties:
+-------------------
+- compatible: should be "fsl,imx8qxp-scu" or "fsl,imx8qm-scu"
+- fsl,mu: a phandle to the Message Unit used by SCU. Should be
+	  one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
+	  to make sure not use the one which is conflict with
+	  other execution environments. e.g. ATF.
Use the mailbox binding even if you don't use the mailbox subsystem.
Looks reasonable. Will change it.

BTW as I said before, the current mailbox binding fixed #mbox-cells to be
at least 1 which is not suitable for i.MX SCU MU as it has only one physical
channel.
Why is that not suitable? If we use #mbox-cells = 1 we can encode the
channel into the second cell. Furthermore, the SCU mode which uses all
channels in a funny way could be another channel id the mu driver could
use to distinguish the different channel/modes. i.e.

#define MU_CHANNEL_0	0
#define MU_CHANNEL_1    1
#define MU_CHANNEL_2    2
#define MU_CHANNEL_3    3
#define MU_CHANNEL_SCU	4


scu {
       compatible = "fsl,imx8qxp-scu";
       fsl,mu = <&lsio_mu1 MU_CHANNEL_SCU>;
};

This would also allow to the MU-SCU-mode driver to coexist with the
regular MU driver for which Oleksij posted a driver.

Sascha

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