From: A.s. Dong Sent: 2018?6?24? 12:24

Copy Andy & Frank,

quoted

-----Original Message-----
From: Michal Vok?? [mailto:michal.vokac at ysoft.com]
Sent: Tuesday, June 12, 2018 11:10 PM
To: linux-gpio at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; Shawn Guo
[off-list ref]; Sascha Hauer [off-list ref];

Fabio

quoted

Estevam [off-list ref]; Rob Herring

[off-list ref];

quoted

devicetree at vger.kernel.org; A.s. Dong [off-list ref];

Fabio

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Estevam [off-list ref]; Shawn Guo [off-list ref];

Stefan

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Agner [off-list ref]; Pengutronix Kernel Team
[off-list ref]; Linus Walleij [off-list ref];
linux- kernel at vger.kernel.org
Subject: Re: [RFC] Configure i.MX6 RGMII pad group control registers
from device tree

On 11.6.2018 14:36, Michal Vok?? wrote:

quoted

Ahoj,

To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = <PIN_FUNC_ID CONFIG> property can be used. Is there any
convenient way to configure the pad group control registers?

The issue is that some bits (DDR_SEL and ODT) in the individual
RGMII pad control registers are read-only. To tweak those parameters
(signal voltage and termination resistors) one need to write to the
pad group control registers for the whole RGMII pad group. Namely
IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII and
IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM. The group registers in

general

quoted

are not accessible from the list in arch/arm/boot/dts/imx6dl-pinfunc.h.

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I could not find any other way to change the group registers than
hacking-in some lines into the imx6q_init_machine(void) function in
arch/arm/mach-imx/mach-imx6q.c source. As I work towards

upstreaming

quoted

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my board this should be done from my device tree or solved in some

universal way.

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Any hints will be much appreciated.
Michal

I figured out this is more "pinctrl-imx.c" than "device-tree" related
so I am kindly adding maintainers of that file in hope somebody will
shed some light to it.

I am diving deeper into the code and it seems there really is no
generic option to set the i.MX6 pad group control registers from device

tree.

quoted

Or am I looking at the problem from a wrong angle?

Yes, there's a few special pad group ctrl registers (e.g. DRAM and RGMII
for mx6q) which are not added In the pinctrl driver support.

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How should we deal with boards that need to configure some pad
characteristics available only through the pad group control registers?

Andy,
How do we handle it internally?

No, we don't handle the pin.
I remembered IC owner said It seems only RGMII 2.5v need to handle the pin.

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I also raised this question at the NXP community forum [1] and get
quite unsatisfying answer so far. I would love to find/implement a
proper and universal solution.

There're probably two ways to do it:
1) handle it in fec driver by parsing a specific property
2) Add a new pad group into pinctrl driver support e.g.
MX6Q_PAD_CTL_GRP_RGMII_TERM
MX6Q_PAD_CTL_GRP_DDR_TYPE_RGMII

I may prefer to 2).

Regards
Dong Aisheng

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Thanks in advance for your time,
Michal

[1]

https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fc
o

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mmunity.nxp.com%2Fthread%2F477464&data=02%7C01%7Caisheng.dong
%4

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0nxp.com%7Ca3e5463eb06a47f1121008d5d0768a04%7C686ea1d3bc2b
4c6fa9

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2cd99c5c301635%7C0%7C1%7C636644129914162495&sdata=xqtBS8uX
%2BSzq

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5m6tbNaLzCkB7ezgHSnyu9GQ3K13cW8%3D&reserved=0