-----Original Message-----
From: Radhey Shyam Pandey
Sent: Wednesday, June 20, 2018 7:13 PM
To: Andrea Merello <redacted>; vkoul at kernel.org;
dan.j.williams at intel.com; Michal Simek [off-list ref]; Appana Durga
Kedareswara Rao [off-list ref]; dmaengine at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
Subject: RE: [PATCH 3/6] dt-bindings: xilinx_dma: add required
xlnx,lengthregwidth property

quoted

-----Original Message-----
From: dmaengine-owner at vger.kernel.org [mailto:dmaengine-
owner at vger.kernel.org] On Behalf Of Andrea Merello
Sent: Wednesday, June 20, 2018 2:07 PM
To: vkoul at kernel.org; dan.j.williams at intel.com; Michal Simek
[off-list ref]; Appana Durga Kedareswara Rao
[off-list ref]; dmaengine at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
Andrea Merello [off-list ref]
Subject: [PATCH 3/6] dt-bindings: xilinx_dma: add required
xlnx,lengthregwidth property

dt-bindings: dmaengine: xilinx_dma

Please also include DT folks.

quoted

The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add DOC for it.

Signed-off-by: Andrea Merello <redacted>
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index a2b8bfaec43c..acecdc5d8d47 100644

--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

@@ -36,6 +36,8 @@ Required properties:

 Required properties for VDMA:
 - xlnx,num-fstores: Should be the number of framebuffers as configured in

h/w.
+Required properties for AXI DMA:
+- xlnx,lengthregwidth: Should be the width of the length register as
configured in h/w.

One suggestion to be inline with IP property naming we can rename
this prop to "xlnx,sg-length-width"? Please take a look at Xilinx tree
we have this feature added in the master branch. It would be good
to consolidate both implementations and upstream. Let me know
if there are any followup queries.

It should be ok to cherrypick 3/6 and 4/6 (xlnx,sg-length-width)
from Xilinx tree and include it in your v2 patch series. 

quoted

 Optional properties:
 - xlnx,include-sg: Tells configured for Scatter-mode in
--
2.17.1

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