Thread (12 messages) 12 messages, 5 authors, 2018-06-02

[PATCH v3 3/5] Documentation: DT: add i.MX EPIT timer binding

From: Vladimir Zapolskiy <hidden>
Date: 2018-05-30 07:27:51
Also in: linux-clk, linux-devicetree

Hi Cl?ment,

On 05/29/2018 08:04 PM, Cl?ment P?ron wrote:
quoted hunk ↗ jump to hunk
From: Cl?ment Peron <redacted>

Add devicetree binding document for NXP's i.MX SoC specific
EPIT timer driver.

Signed-off-by: Cl?ment Peron <redacted>
---
 .../devicetree/bindings/clock/imx6q,epit.txt  | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt
diff --git a/Documentation/devicetree/bindings/clock/imx6q,epit.txt b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
new file mode 100644
index 000000000000..a84a60c6ae35
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
The file should be renamed to a more generic name like 'imx,epit.txt'
or 'imx31,epit.txt'.

Also note that the folder is incorrectly selected, it must be
Documentation/devicetree/bindings/timer/
quoted hunk ↗ jump to hunk
@@ -0,0 +1,24 @@
+Binding for the i.MX6 EPIT timer
Let's change it to 'Binding for the i.MX EPIT timer'.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "fsl,imx6q-epit"
Compatible should be "fsl,imx31-epit", i.MX31 SoC seems to be the first
one in the series, which has the timer module.

There should be added more compatibles specific to later SoC versions.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: Should contain EPIT controller interrupt
+- clocks: list of clock specifiers, must contain an entry for each required
+  entry in clock-names
+- clock-names : should include entries "ipg", "per"
+
+Example:
+	epit1: epit at 20d0000 {
+		compatible = "fsl,imx6q-epit";
For i.MX6Q example a list of compatibles should be updated like

	compatible = "fsl,imx6q-epit", "fsl,imx31-epit";
+		reg = <0x020d0000 0x4000>;
+		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX6QDL_CLK_EPIT1>,
+			<&clks IMX6QDL_CLK_IPG_PER>;
+		clock-names = "ipg", "per";
It looks like "ipg" and "per" clocks are swapped, please double check it.
+	};
--
With best wishes,
Vladimir
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