[PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
STALE3046d
REVIEWED: 6 (6M)
From: david@lechnology.com (David Lechner)
Date: 2018-05-25 18:13:22
Also in:
linux-clk, lkml
Subsystem:
common clk framework, the rest, ti davinci series clock driver · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Linus Torvalds, David Lechner
1 review trailer (1 from subsystem maintainers).
From: Sekhar Nori <redacted> PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori <redacted> Reviewed-by: David Lechner <david@lechnology.com> --- drivers/clk/davinci/pll-dm646x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
index a61cc3256418..0ae827e3ce80 100644
--- a/drivers/clk/davinci/pll-dm646x.c
+++ b/drivers/clk/davinci/pll-dm646x.c@@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = { .flags = 0, }; -SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0); +SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED); int dm646x_pll2_init(struct device *dev, void __iomem *base) {
--
2.17.0