Thread (42 messages) 42 messages, 6 authors, 2018-06-05

[PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents

From: Jernej Škrabec <hidden>
Date: 2018-05-19 07:12:02
Also in: dri-devel, linux-clk, linux-devicetree, lkml

Hi,

Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej ?krabec wrote:
quoted
quoted
And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
lookup pll-2 either.
It is highly unlikely this will be higher than 2, at least for this HDMI
PHY, since it has only 1 bit reserved for parent selection. But since I
have to fix it, I'll add ">= 2"
If we're only going to have two parents at most, ever, why don't we
had just a single other boolean. This would be less intrusive, and we
wouldn't have to check for those corner cases.
It seems that usage of "bool" data type in structures is not wanted anymore 
according to checkpatch and this: https://lkml.org/lkml/2017/11/21/384

I guess I'll use "unsigned int" as recommended by Linus and named it 
"has_second_parent" to be unambigous that it's boolean in reality.

Best regards,
Jernej
quoted
BTW, I'll resend fixed version of this patch for my R40 HDMI series, since
there is nothing to hold it back, unlike for this.
Awesome, thanks!
Maxime

--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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